Testing and Evaluation of the Configurable Fault Tolerant Processor (CFTP) for Space-Based Applications

With the complexity of digital systems, reliability considerations are important. In many digital systems it is desirable to continuously monitor, exercise, and test the system to determine whether it is performing as desired. Such monitoring may enable automatic detection of failures via periodic testing or through the use of codes and checking circuits (e.g., built-in self-testing). While any complex system requires testing to ensure satisfactory performance, satellite systems require extensive testing for two additional reasons: they operate in an environment considerably different from that in which they were built, and after launch they are inaccessible to routine maintenance and repair. Because of these unique requirements, a specific solution is needed: a self- contained, autonomous, self-testing circuit. The focus of this thesis is the design and development of a series of Built-In Self-Tests (BISTs) for use with the Configurable Fault Tolerant Processor (CFTP). The results of this thesis are two detailed designs for a Random Access Memory (RAM) BIST and a Read-Only Memory (ROM) BIST, as well as a conceptual design for a Field Programmable Gate Array (FPGA) BIST. These designs are stored on board the CFTP and are made to operate remotely and autonomously. Together, these BISTs provide a means to monitor, exercise, and test the CFTP components and thus facilitate a reliable design. (13 tables, 50 figures, 35 refs.)Naval Postgraduate School Monterey CA is the author of 'Testing and Evaluation of the Configurable Fault Tolerant Processor (CFTP) for Space-Based Applications' with ISBN 9781423514381 and ISBN 1423514386.